From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id XAA08832; Thu, 8 Jul 2004 23:28:44 +0200 (MET DST) X-Authentication-Warning: pauillac.inria.fr: majordomo set sender to owner-caml-list@pauillac.inria.fr using -f Received: from concorde.inria.fr (concorde.inria.fr [192.93.2.39]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id XAA09509 for ; Thu, 8 Jul 2004 23:28:43 +0200 (MET DST) Received: from herd.plethora.net (herd.plethora.net [205.166.146.1]) by concorde.inria.fr (8.12.10/8.12.10) with ESMTP id i68LSfSH019887 for ; Thu, 8 Jul 2004 23:28:42 +0200 Received: from bhurt.plethora.net (bhurt.plethora.net [205.166.146.49]) by herd.plethora.net (8.11.6/8.10.1) with ESMTP id i68LSWi16913; Thu, 8 Jul 2004 16:28:37 -0500 (CDT) Date: Thu, 8 Jul 2004 16:35:20 -0500 (CDT) From: Brian Hurt X-X-Sender: bhurt@localhost.localdomain To: "Brandon J. Van Every" cc: caml Subject: Re: [Caml-list] tail recursion and register poor Intel architecture In-Reply-To: Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Miltered: at concorde with ID 40EDBC89.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Loop: caml-list@inria.fr X-Spam: no; 0.00; caml-list:01 recursion:01 brandon:99 intel's:01 vectors:01 scalars:01 intel's:01 rescue:99 counted:01 -bit:01 -bit:01 backward:02 stack:02 stack:02 pointer:03 Sender: owner-caml-list@pauillac.inria.fr Precedence: bulk On Thu, 8 Jul 2004, Brandon J. Van Every wrote: > Or implement more of what Intel's crufty architecture actually offers. > For instance, supporting SSE would provide 8 additional 32-bit FPU > registers. If you're using the MMX/SSE[123] registers, you can not be using the x87 registers. In addition, to move values between these registers (or the x87 registers) and the normal integer registers, you have to go via memory- i.e. write the value out to memory and read them back in again into the other register. At which point you might as well be throwing them on the stack. The large print giveth, and the small print taketh away. > One doesn't have to use use the XMM registers for vectors, > they could be used as scalars, and that's the more straightforward > benefit of SSE architecture. SSE2 allows for 64-bit FPU registers and > also integer registers, of size 32-bit and 64-bit IIRC (but I haven't > much cared about integer code). SSE2 is also only available on the P4s and the Opterons/Athlon-64s (AMD is the current crown holder for cool code names and dorky release names, having taken it away from HP. Hammers and Snakes- cool code names. Sempron? Give me a break). Those of us with older computers would like to keep backward compatibility. > For the record, I hate Intel's architectures. They were talking about > Merced when I was writing real code on DEC Alpha. Alpha is dead for > marketing reasons, not technical ones. Meanwhile, Itanium is still > handwaving. Yes, but now it's the desperate handwaving of people trying to flag down a rescue helicopter. > > AMD also offers more registers on their newest chips. I'm too fazed to > remember the details right now; I do recall twice as many FPU registers. > The new iAMD-64 architecture in 64-bit mode has 16 general purpose registers (of which 14 are usable as such- the stack pointer and base pointer are both counted as general purpose registers), and 16 fp registers (usable as both x87 and MMX/SSE[123] registers). -- "Usenet is like a herd of performing elephants with diarrhea -- massive, difficult to redirect, awe-inspiring, entertaining, and a source of mind-boggling amounts of excrement when you least expect it." - Gene Spafford Brian ------------------- To unsubscribe, mail caml-list-request@inria.fr Archives: http://caml.inria.fr Bug reports: http://caml.inria.fr/bin/caml-bugs FAQ: http://caml.inria.fr/FAQ/ Beginner's list: http://groups.yahoo.com/group/ocaml_beginners