From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id AAA12781; Fri, 9 Jul 2004 00:52:00 +0200 (MET DST) X-Authentication-Warning: pauillac.inria.fr: majordomo set sender to owner-caml-list@pauillac.inria.fr using -f Received: from nez-perce.inria.fr (nez-perce.inria.fr [192.93.2.78]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id AAA12578 for ; Fri, 9 Jul 2004 00:51:59 +0200 (MET DST) Received: from outbound28-2.lax.untd.com (outbound28-2.lax.untd.com [64.136.28.160]) by nez-perce.inria.fr (8.12.10/8.12.10) with SMTP id i68MpvEV021143 for ; Fri, 9 Jul 2004 00:51:58 +0200 Received: from outbound28-2.lax.untd.com (smtp04.lax.untd.com [10.130.24.124]) by smtpout06.lax.untd.com with SMTP id AABAQ5V9HAKEXCV2 for (sender ); Thu, 8 Jul 2004 15:51:19 -0700 (PDT) Received: (qmail 11125 invoked from network); 8 Jul 2004 22:50:54 -0000 Received: from unknown (HELO vangogh) (66.52.239.74) by smtp04.lax.untd.com with SMTP; 8 Jul 2004 22:50:54 -0000 From: "Brandon J. Van Every" To: "caml" Subject: RE: [Caml-list] tail recursion and register poor Intel architecture Date: Thu, 8 Jul 2004 16:01:05 -0700 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook IMO, Build 9.0.6604 (9.0.2911.0) In-Reply-To: X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1409 Importance: Normal X-ContentStamp: 15:7:2043967921 X-UNTD-OriginStamp: CI84cOLHFqh7Zd2QWkwvEFvwyO3T/pIsPQZphDk9MRhwKNmwrcJMDOGmjVfdXZ4D X-Miltered: at nez-perce with ID 40EDD00D.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Loop: caml-list@inria.fr X-Spam: no; 0.00; brandon:99 caml-list:01 recursion:01 brandon:99 intel's:01 incompatible:01 model:01 caml-list:01 bayesian:01 crap:01 crap:01 implements:01 -bit:01 float:02 backward:02 Sender: owner-caml-list@pauillac.inria.fr Precedence: bulk Brian Hurt wrote: > On Thu, 8 Jul 2004, Brandon J. Van Every wrote: > > > Or implement more of what Intel's crufty architecture > actually offers. > > For instance, supporting SSE would provide 8 additional 32-bit FPU > > registers. > > If you're using the MMX/SSE[123] registers, you can not be > using the x87 registers. That is true/false. These are *not* synonymous sets of registers. MMX registers are incompatible with the x87 FPU as you describe, because they're aliases/repurposings of the x87 FPU registers. The *XMM* registers, associated with SSE/SSE2, are entirely separate registers. You can most certainly use the x87 FPU simultaneously with those, no special instruction state dances required. > In addition, to move values between these registers (or the > x87 registers) and the normal integer registers, you have to go via > memory- i.e. write the value out to memory and read them back > in again into the other register. At which point you might as well be > throwing them on the stack. Well, you could pass the first 6 integer arguments via the normal registers, the first 8 floating point arguments via the x87 FPU, and the next 8 integer or float arguments via the XMM registers. The values wouldn't always be interoperable, you'd have to go through memory in various cases, but it's better than nothing getting passed in registers at all. In any event I think this is more useful for FPU than integer code. > SSE2 is also only available on the P4s and the > Opterons/Athlon-64s Yes I mentioned the P4 requirement. So what? P4s have been around for quite some time now. It of course would be a conditional compilation flag, but I see no reason why one should fear a paucity of SSE2 support nowadays. My late model 866 MHz P-III is 4 year old technology now. A functional workhorse, but obsolescent. > Those of us with older computers would like > to keep backward compatibility. Those of you with particularly old computers are cheap-ass bastards who should afford buying a new one every 6 years or so. :-) I do believe in buying "behind the power curve," but come on, by the time anybody actually implements what I'm talking about the P-IIIs will be mostly gone. Cheers, www.indiegamedesign.com Brand*n Van Every S*attle, WA Praise Be to the caml-list Bayesian filter! It blesseth my postings, it is evil crap! evil crap! evil crap! ------------------- To unsubscribe, mail caml-list-request@inria.fr Archives: http://caml.inria.fr Bug reports: http://caml.inria.fr/bin/caml-bugs FAQ: http://caml.inria.fr/FAQ/ Beginner's list: http://groups.yahoo.com/group/ocaml_beginners