From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id RAA01675; Thu, 12 Aug 2004 17:23:01 +0200 (MET DST) X-Authentication-Warning: pauillac.inria.fr: majordomo set sender to owner-caml-list@pauillac.inria.fr using -f Received: from concorde.inria.fr (concorde.inria.fr [192.93.2.39]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id RAA02072 for ; Thu, 12 Aug 2004 17:23:00 +0200 (MET DST) Received: from kaiserslautern1.lms-gmbh.de (kaiserslautern1.lms-gmbh.de [212.43.68.201]) by concorde.inria.fr (8.12.10/8.12.10) with ESMTP id i7CFMxRM011744 for ; Thu, 12 Aug 2004 17:22:59 +0200 Received: by mail.lms-gmbh.de with Internet Mail Service (5.5.2653.19) id ; Thu, 12 Aug 2004 17:22:59 +0200 Message-ID: From: "Bauer, Christoph" To: caml-list@inria.fr Subject: AW: [Caml-list] The tag bit Date: Thu, 12 Aug 2004 17:22:53 +0200 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C48080.3CCEEDE0" X-Miltered: at concorde with ID 411B8B53.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Loop: caml-list@inria.fr X-Spam: no; 0.00; bauer:01 bauer:01 caml-list:01 65.:99 caml-list:01 W4:99 65.:99 garbage:01 garbage:01 collector:02 collector:02 address:96 address:96 pointer:03 anyway:05 Sender: owner-caml-list@pauillac.inria.fr Precedence: bulk This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. ------_=_NextPart_001_01C48080.3CCEEDE0 Content-Type: text/plain > Well, I can see several reasons : > * processors like powers of two, especially when it comes > to the size > of a memory address, because of cache issues, so you'd better > make it 32 > or 64 words than 33 or 65. > * If the tag bit can be anywhere in a word you have to spend extra > time to extract it, whereas when it is at a fixed place, > especially LSB > or MSB, it is very cheap and easy. > * You would need two registers to access a value and its > tag instead > of one, and registers are very precious, at least on IA-32 > architectures. But who needs the tag bit? Only the garbage collector. Maybe it's an advantage to see 32 tag bits as a whole, e.g. the question "does the block contains any pointer" can be calculated bit-parallel. Anyway the garbage collector could works on blocks and needs just one additional memory access per block. Regards, Christoph Bauer ------_=_NextPart_001_01C48080.3CCEEDE0 Content-Type: text/html AW: [Caml-list] The tag bit

>     Well, I can see several reasons :
>   * processors like powers of two, especially when it comes
> to the size
> of a memory address, because of cache issues, so you'd better
> make it 32
> or 64 words than 33 or 65.
>   * If the tag bit can be anywhere in a word you have to spend extra
> time to extract it, whereas when it is at a fixed place,
> especially LSB
> or MSB, it is very cheap and easy.
>   * You would need two registers to access a value and its
> tag instead
> of one, and registers are very precious, at least on IA-32
> architectures.

But who needs the tag bit? Only the garbage collector. Maybe it's
an advantage to see 32 tag bits as a whole, e.g. the question
"does the block contains any pointer" can be calculated bit-parallel.
Anyway the garbage collector could works on blocks and needs
just one additional memory access per block.

Regards,
Christoph Bauer

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