From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail4-relais-sop.national.inria.fr (mail4-relais-sop.national.inria.fr [192.134.164.105]) by walapai.inria.fr (8.13.6/8.13.6) with ESMTP id p8PHuSum016712 for ; Sun, 25 Sep 2011 19:56:28 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AhIEAO1qf07RVdU2imdsb2JhbABCDqVPghkIFAEBAQoJDQcSBiIEgVEBBQEBDwIJIwETCAoCEgMSEDshAQERAQUBIQISCBqkGgqLTIJcg2U7iG4CAwaHBQSHcotgiheCcj2DNlU X-IronPort-AV: E=Sophos;i="4.68,440,1312149600"; d="scan'208";a="110425312" Received: from mail-yw0-f54.google.com ([209.85.213.54]) by mail4-smtp-sop.national.inria.fr with ESMTP/TLS/RC4-SHA; 25 Sep 2011 19:56:21 +0200 Received: by ywp17 with SMTP id 17so5972520ywp.27 for ; Sun, 25 Sep 2011 10:56:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=TbmIkuHOklvAlg0ndM6G+1493WqjJgtNcYo1JsCNrX4=; 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orna@cs.technion.ac.il, ask@cs.tut.fi, naumann@cs.stevens-tech.edu, myers@ee.elen.utah.edu, elena@ele.kth.se, gopi@csa.iisc.ernet.in, shengru@cs.uno.edu, stoller@cs.sunysb.edu, natali@research.bell-labs.com, depasse@info.ucl.ac.be, manish@cityline.ru, sistla@eecs.uic.edu, fabio@colorado.edu, tamirh@cs.technion.ac.il, David.Sinclair@compapp.dcu.ie, namla@cs.utexas.edu, sriram@microsoft.com, rehof@microsoft.com, schmidt@cis.ksu.edu, Richard.St-Denis@dmi.usherb.ca, adriana.maggiore@transeda.com, stephane@umich.edu, fmavaddat@uwaterloo.ca, end419@yahoo.co.uk, bywang@saul.cis.upenn.edu, yrodeh@wisdom.weizmann.ac.il, dawnsong@cs.berkeley.edu, hanac@cs.huji.ac.il, alexander.s.levin@intel.com, yossef.levy@intel.com, basin@informatik.uni-freiburg.de, e02716@jp.ibm.com, erichm@cadence.com, pargon@cadence.com, yonezaki@cs.titech.ac.jp, Xavier.Leroy@inria.fr Content-Type: multipart/alternative; boundary=000e0cd5c72a84b74d04adc7c192 X-Validation-by: mvelev@gmail.com Subject: [Caml-list] CFPs: abstracts due today for CFV'11 Workshop at ICCAD'11 --000e0cd5c72a84b74d04adc7c192 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Call for papers: CFV'11: Seventh International Workshop on Constraints in Formal Verification DoubleTree Hotel, San Jose, California, November 10, 2011 A satellite event of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 2011 Abstract submission deadline: September 25, 2011 Paper submission deadline: September 30, 2011 Date of workshop: November 10, 2011 (right after ICCAD=9211) Overview --------------------------------------------- Formal verification is of crucial significance in the development of hardware and software systems. In the last few years, tremendous progress was made in both the speed and capacity of constraint technology. Most notably, SAT solvers have become orders of magnitude faster and capable of handling problems that are orders of magnitude bigger, thus enabling the formal verification of more complex computer systems. As a result, the formal verification of hardware and software has become a promising area for research and industrial applications. The main goals of the Constraints in Formal Verification workshop are to bring together researchers from the CSP/SAT and the formal verification communities, to describe new applications of constraint technology to formal verification, to disseminate new challenging problem instances, and to propose new dedicated algorithms for hard formal verification problems. This workshop will be of interest to researchers from both academia and industry, working on constraints or on formal verification and interested in the application of constraints to formal verification. Scope --------------------------------------------- The scope of the workshop includes topics related to the application of constraint technology to formal verification, namely: - application of constraint solvers to hardware verification; - application of constraint solvers to software verification; - dedicated solvers for formal verification problems; - challenging formal verification problems. Submissions --------------------------------------------- Submissions should be in the IEEE format and in one of the following types: - a regular paper of up to 6 pages; - a short paper of up to 4 pages, describing an industrial experience. Workshop papers should be submitted electronically in pdf format. Abstract and paper submissions should be e-mailed to the workshop chair at: mvelev@gmail.com Important Dates --------------------------------------------- - abstract submission deadline: September 25, 2011 - paper submission deadline: September 30, 2011 - notification of acceptance: October 10, 2011 - camera-ready version deadline: October 25, 2011 - workshop date: November 10, 2011 Invited Speaker --------------------------------------------- Carl Seger, Intel, U.S.A. Natarajan Shankar, SRI, U.S.A. Workshop Chair --------------------------------------------- Miroslav Velev, Aries Design Automation, U.S.A. Program Committee -------------------------------------------- Maciej Ciesielski, University of Massachusetts, U.S.A. Masahiro Fujita, University of Tokyo, Japan Alex Groce, Oregon State University, U.S.A. Daniel Grosse, University of Bremen, Germany Michael Hsiao, Virginia Tech, U.S.A. Sumit Jha, University of Central Florida, U.S.A. Robert Jones, Intel, U.S.A. Peter-Michael Seidel, AMD, U.S.A. Andreas Veneris, University of Toronto, Canada Markus Wedler, University of Kaiserslautern, Germany --000e0cd5c72a84b74d04adc7c192 Content-Type: text/html; charset=windows-1252 Content-Transfer-Encoding: quoted-printable

Call for papers:
=A0
CFV'11:=A0 Seventh International Workshop= on Constraints in Formal Verification
DoubleTree Hotel, San Jose, Calif= ornia, November 10, 2011
A satellite event of the IEEE/ACM International= Conference on Computer-Aided Design (ICCAD). 2011
=A0
=A0
Abstract submission deadline:=A0 September 25, 2011
Paper = submission deadline:=A0 September 30, 2011
=A0
Date of workshop: Nove= mber 10, 2011 (right after ICCAD=9211)


Overview
---------------------------------------------
Formal = verification is of crucial significance in the development of
hardware a= nd software systems. In the last few years, tremendous
progress was made= in both the speed and capacity of constraint
technology. Most notably, SAT solvers have become orders of magnitude
fa= ster and capable of handling problems that are orders of magnitude
bigge= r, thus enabling the formal verification of more complex computer
system= s. As a result, the formal verification of hardware and software
has become a promising area for research and industrial applications.
Th= e main goals of the Constraints in Formal Verification workshop are
to b= ring together researchers from the CSP/SAT and the formal
verification c= ommunities, to describe new applications of constraint
technology to formal verification, to disseminate new challenging
proble= m instances, and to propose new dedicated algorithms for hard
formal ver= ification problems.
This workshop will be of interest to researchers fro= m both academia
and industry, working on constraints or on formal verification and
inter= ested in the application of constraints to formal verification.


Scope
---------------------------------------------
The scope = of the workshop includes topics related to the application
of constraint= technology to formal verification, namely:
- application of constraint = solvers to hardware verification;
- application of constraint solvers to software verification;
- dedicate= d solvers for formal verification problems;
- challenging formal verific= ation problems.


Submissions
---------------------------------------------
Subm= issions should be in the IEEE format and in one of the following types:
= - a regular paper of up to 6 pages;
- a short paper of up to 4 pages, de= scribing an industrial experience.
Workshop papers should be submitted electronically in pdf format.
Abstra= ct and paper submissions should be e-mailed to the workshop chair at: mvelev@gmail.com


Important Dates
---------------------------------------------
= - abstract submission deadline:=A0 September 25, 2011
- paper submission= deadline:=A0 September 30, 2011
- notification of acceptance:=A0 Octobe= r 10, 2011
- camera-ready version deadline: October 25, 2011
- workshop date:=A0 No= vember 10, 2011

=A0

Invited Speaker
---------------------------------------------
Carl= Seger, Intel, U.S.A.
Natarajan Shankar, SRI, U.S.A.

=A0


Workshop Chair
---------------------------------------------
M= iroslav Velev, Aries Design Automation, U.S.A.

=A0

Program Committee
--------------------------------------------
M= aciej Ciesielski, University of Massachusetts, U.S.A.
Masahiro Fujita, U= niversity of Tokyo, Japan
Alex Groce, Oregon State University, U.S.A.
Daniel Grosse, University of Bremen, Germany
Michael Hsiao, Virginia Tec= h, U.S.A.
Sumit Jha, University of Central Florida, U.S.A.
Robert Jon= es, Intel, U.S.A.
Peter-Michael Seidel, AMD, U.S.A.
Andreas Veneris, = University of Toronto, Canada
Markus Wedler, University of Kaiserslautern, Germany
=A0
--000e0cd5c72a84b74d04adc7c192--