From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on yquem.inria.fr X-Spam-Level: * X-Spam-Status: No, score=1.1 required=5.0 tests=AWL,SPF_NEUTRAL autolearn=disabled version=3.1.3 Received: from concorde.inria.fr (concorde.inria.fr [192.93.2.39]) by yquem.inria.fr (Postfix) with ESMTP id F33B8BC6B for ; Thu, 6 Sep 2007 22:59:45 +0200 (CEST) Received: from nz-out-0506.google.com (nz-out-0506.google.com [64.233.162.232]) by concorde.inria.fr (8.13.6/8.13.6) with ESMTP id l86Kxjam022491 for ; Thu, 6 Sep 2007 22:59:45 +0200 Received: by nz-out-0506.google.com with SMTP id z3so200628nzf for ; Thu, 06 Sep 2007 13:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=beta; h=domainkey-signature:received:received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; bh=D5j1U7rEACzFTSpyRT8XLI/79aLNP7IW6tZh1JtIFiY=; b=K6tEoiCkau9tIYeG2WzvSACjPEfeyGitU4AutN9bnH1q2DGhBn5W7bnsUCowUM+9ExmMZmiD3rA5qPGhxf4ex3DpRzgTT2veMH6p41WwxPmSnDjmCBxn79RlCVwWZHWClBM1DzZ5S6ULloZYStUPnUxnuJ1LhG0MCOvxgF1Lm4Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=beta; h=received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=TpmPKNRMNaZN4ZbIMOU6N+TqWDyslAirLcQ5+mZI9FyMDYA+DxuEVEvQgT0cBAjMJFSB7uJVBQeW9sVQabdsmgzUfhbmY9TTAuzmop28y43sL1OQHVgRp3XcXqVP7x9WuxxWf22oPze9CS6vjJG6tukCe22hr8lX0+xoOxkuus4= Received: by 10.115.95.1 with SMTP id x1mr1008599wal.1189112383184; Thu, 06 Sep 2007 13:59:43 -0700 (PDT) Received: by 10.114.203.16 with HTTP; Thu, 6 Sep 2007 13:59:43 -0700 (PDT) Message-ID: <875c7e070709061359r1b89580bx2be52a770b6b1271@mail.gmail.com> Date: Thu, 6 Sep 2007 16:59:43 -0400 From: "Chris King" To: "Richard Jones" Subject: Re: [Caml-list] More registers in modern day CPUs Cc: "Caml List" In-Reply-To: <20070906204524.GB10798@furbychan.cocan.org> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <875c7e070709060755r1d0d099ds30a25ea78d0fd85a@mail.gmail.com> <20070906204524.GB10798@furbychan.cocan.org> X-j-chkmail-Score: MSGID : 46E06A41.001 on concorde : j-chkmail score : X : 0/20 1 0.000 -> 1 X-Miltered: at concorde with ID 46E06A41.001 by Joe's j-chkmail (http://j-chkmail . ensmp . fr)! X-Spam: no; 0.00; acted:98 wrote:01 caml-list:01 structures:02 slower:02 slower:02 notion:04 chris:06 chris:06 feasible:07 processor:08 registers:08 registers:08 john:08 replaces:09 On 9/6/07, Richard Jones wrote: > The 6502 was a successful 8-bit processor where the "on chip" > registers were very few, but the first part of RAM acted as memory > mapped registers. I grew up on the 6502... beautiful architecture :) > This is not feasible in current chips for a whole variety of reasons, > starting with the fact that current RAM is hundreds of times slower > than registers (and even L1 cache is 4-8 times slower). Right, hence my notion of "register-level cache"... something smaller and faster than L1 that replaces registers entirely. (John Harrison got what I was on about.) I will check out that book though... I know very little about cache structures. - Chris