From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on yquem.inria.fr X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=AWL,HTML_MESSAGE autolearn=disabled version=3.1.3 Received: from discorde.inria.fr (discorde.inria.fr [192.93.2.38]) by yquem.inria.fr (Postfix) with ESMTP id 6C435BC6B for ; Thu, 6 Sep 2007 17:54:56 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by discorde.inria.fr (8.13.6/8.13.6) with ESMTP id l86FssDD017615 for ; Thu, 6 Sep 2007 17:54:55 +0200 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 06 Sep 2007 08:54:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.20,216,1186383600"; d="scan'208,217";a="273288289" Received: from orsmsx335.jf.intel.com ([10.22.226.40]) by azsmga001.ch.intel.com with ESMTP; 06 Sep 2007 08:54:50 -0700 Received: from orsmsx419.amr.corp.intel.com ([10.22.226.88]) by orsmsx335.jf.intel.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 6 Sep 2007 08:54:50 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C7F09E.42271241" Subject: RE: [Caml-list] More registers in modern day CPUs Date: Thu, 6 Sep 2007 08:54:49 -0700 Message-ID: <509223F0BF55E74FA1247D17207E7A0C01D75893@orsmsx419.amr.corp.intel.com> In-Reply-To: <46E01A27.1070207@janestcapital.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [Caml-list] More registers in modern day CPUs Thread-Index: AcfwmWmX5Oam0l15SsiClcciYLJ1jgAA/TWQ References: <875c7e070709060755r1d0d099ds30a25ea78d0fd85a@mail.gmail.com> <46E01A27.1070207@janestcapital.com> From: "Harrison, John R" To: "Caml-list List" X-OriginalArrivalTime: 06 Sep 2007 15:54:50.0634 (UTC) FILETIME=[4202FEA0:01C7F09E] X-j-chkmail-Score: MSGID : 46E022CE.001 on discorde : j-chkmail score : XX : 5/20 0 0.000 -> 2 X-Miltered: at discorde with ID 46E022CE.001 by Joe's j-chkmail (http://j-chkmail . ensmp . fr)! X-Spam: no; 0.00; itanium:01 itanium:01 sony:98 toshiba:98 sony:98 toshiba:98 wrote:01 wrote:01 caml-list:01 explicitly:02 explicitly:02 indexing:02 indexing:02 arial:96 arial:96 This is a multi-part message in MIME format. ------_=_NextPart_001_01C7F09E.42271241 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Chris King wrote: =20 | This makes me wonder... why have registers to begin with? I wonder how | feasible a chip with a, say, 256-byte "register-level" cache would be. =20 and Brian Hurt said: =20 | Such chips exist. The Itanium is one example. =20 The Itanium is indeed an example of an architecture with a relatively large number of registers, and where the register file has certain memory-like features such as automatic indexing offsets. =20 But as I understood it, Chris was proposing the opposite: have few or no registers, and rely on main memory instead, with some extra fast inner level cache to speed it up. =20 Both the old Inmos Transputer and the the more recent IBM/Sony/Toshiba Cell processor have/had a dedicated area of fast memory, rather like a giant memory-based register file. In each case this is explicitly visible to user-level software rather than being a cache in the usual sense. =20 John. =20 ------_=_NextPart_001_01C7F09E.42271241 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Chris King = wrote:

| This makes me wonder... why have registers to begin with? I wonder how

| feasible a chip with a, say, = 256-byte "register-level" cache would be.

and Brian Hurt = said:

| Such chips exist. The = Itanium is one example.

The Itanium is indeed an example of = an architecture with a relatively

large number of registers, and = where the register file has certain

memory-like features such as = automatic indexing offsets.

But as I understood it, Chris was proposing the opposite: have few or

no registers, and rely on main = memory instead, with some extra fast

inner level cache to speed it = up.

Both the old Inmos Transputer and = the the more recent IBM/Sony/Toshiba

Cell processor have/had a dedicated = area of fast memory, rather like a

giant memory-based register file. = In each case this is explicitly visible to

user-level software rather than = being a cache in the usual sense.

John.

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