Chris King wrote:

 

| This makes me wonder... why have registers to begin with?  I wonder
how

| feasible a chip with a, say, 256-byte "register-level" cache would be.

 

and Brian Hurt said:

 

| Such chips exist.  The Itanium is one example.

 

The Itanium is indeed an example of an architecture with a relatively

large number of registers, and where the register file has certain

memory-like features such as automatic indexing offsets.

 

But as I understood it, Chris was proposing the opposite: have few or

no registers, and rely on main memory instead, with some extra fast

inner level cache to speed it up.

 

Both the old Inmos Transputer and the the more recent IBM/Sony/Toshiba

Cell processor have/had a dedicated area of fast memory, rather like a

giant memory-based register file. In each case this is explicitly
visible to

user-level software rather than being a cache in the usual sense.

 

John.