From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on yquem.inria.fr X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=AWL,DNS_FROM_RFC_ABUSE autolearn=disabled version=3.1.3 Received: from mail2-relais-roc.national.inria.fr (mail2-relais-roc.national.inria.fr [192.134.164.83]) by yquem.inria.fr (Postfix) with ESMTP id C02DCBC6B for ; Thu, 10 Jan 2008 14:56:18 +0100 (CET) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: Ah4FADezhUdDWxLC/2dsb2JhbACBVqgx X-IronPort-AV: E=Sophos;i="4.24,266,1196636400"; d="scan'208";a="5907060" Received: from ip67-91-18-194.z18-91-67.customer.algx.net (HELO server1.bertec.net) ([67.91.18.194]) by mail2-smtp-roc.national.inria.fr with ESMTP; 10 Jan 2008 14:56:32 +0100 Received: from kuba.bertec.net (kuba.bertec.net [192.168.2.16]) by server1.bertec.net (Postfix) with ESMTP id 30AF7105830 for ; Thu, 10 Jan 2008 08:56:17 -0500 (EST) From: Kuba Ober To: caml-list@yquem.inria.fr Subject: Re: [Caml-list] ocaml doesn't need to optimize on amd64?? Date: Thu, 10 Jan 2008 08:56:16 -0500 User-Agent: KMail/1.9.6 (enterprise 0.20071123.740460) References: <200801090922.00231.ober.14@osu.edu> <20080110024359.GA15544@mulga.csse.unimelb.edu.au> In-Reply-To: <20080110024359.GA15544@mulga.csse.unimelb.edu.au> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200801100856.16411.ober.14@osu.edu> X-Spam: no; 0.00; ocaml:01 ocaml:01 gcc:01 intel's:01 cheers:01 wrote:01 wrote:01 stack:01 caml-list:01 emulate:01 data:02 opcodes:03 notion:04 processors:04 accessed:05 On Wednesday 09 January 2008, you wrote: > On Wed, Jan 09, 2008 at 09:22:00AM -0500, Kuba Ober wrote: > > Jon & al, > > > > why do you think that OCaml doesn't need to do certain > > optimizations on amd64? Or does it apply only to 64 bit mode? > > I run my benchmarks on amd64 (in 32 bit mode) and OCaml is worse > > off than gcc. > > Register pressure. The extra eight registers in AMD64 make a huge > difference to a lot of code generators. Of course, to access them > you need to run in 64 bit mode. Don't current x32 processors "emulate" extra registers anyway? I don't know what's the preferred way of telling the on-chip code dissector that you intend the data to say in virtual registers, but it must be something simple, like common, fixed memory locations or stack locations accessed in a certain way. I'm sure if you google on Intel's site you'll find it. In any event, the x32 chips have a notion of "many" virtual registers, it's just the old x32 opcodes that don't have it. Isn't it so? Cheers, Kuba