From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on yquem.inria.fr X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=AWL autolearn=disabled version=3.1.3 Received: from concorde.inria.fr (concorde.inria.fr [192.93.2.39]) by yquem.inria.fr (Postfix) with ESMTP id 2D403BC6B for ; Thu, 6 Sep 2007 22:48:09 +0200 (CEST) Received: from furbychan.cocan.org (furbychan.cocan.org [80.68.91.176]) by concorde.inria.fr (8.13.6/8.13.6) with ESMTP id l86Km80g019262 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO) for ; Thu, 6 Sep 2007 22:48:08 +0200 Received: from rich by furbychan.cocan.org with local (Exim 3.35 #1 (Debian)) id 1ITOGm-0004e0-00 for ; Thu, 06 Sep 2007 21:48:08 +0100 Date: Thu, 6 Sep 2007 21:48:08 +0100 To: caml-list@inria.fr Subject: Re: [Caml-list] More registers in modern day CPUs Message-ID: <20070906204808.GC10798@furbychan.cocan.org> References: <875c7e070709060755r1d0d099ds30a25ea78d0fd85a@mail.gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <875c7e070709060755r1d0d099ds30a25ea78d0fd85a@mail.gmail.com> User-Agent: Mutt/1.5.9i From: Richard Jones X-Miltered: at concorde with ID 46E06788.002 by Joe's j-chkmail (http://j-chkmail . ensmp . fr)! X-Spam: no; 0.00; wikipedia:01 wiki:01 acted:98 wrote:01 wrote:01 caml-list:01 emulate:01 slower:02 slower:02 thu:05 sep:06 chris:06 feasible:07 feasible:07 red:92 On Thu, Sep 06, 2007 at 10:55:20AM -0400, Chris King wrote: > On 9/6/07, Tom wrote: > > However, would it be possible to "emulate" cpu registers using software? By > > keeping registers in the main memory, but accessing them often enough to > > keep them in primary cache? That would be quite fast I believe... > > This makes me wonder... why have registers to begin with? I wonder > how feasible a chip with a, say, 256-byte "register-level" cache would The 6502 was a successful 8-bit processor where the "on chip" registers were very few, but the first part of RAM acted as memory mapped registers. http://en.wikipedia.org/wiki/6502 This is not feasible in current chips for a whole variety of reasons, starting with the fact that current RAM is hundreds of times slower than registers (and even L1 cache is 4-8 times slower). You should read "Computer Architecture: A Quantitative Approach" by Hennessy & Patterson. Rich. -- Richard Jones Red Hat