From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id JAA23864; Fri, 11 Oct 2002 09:52:46 +0200 (MET DST) X-Authentication-Warning: pauillac.inria.fr: majordomo set sender to owner-caml-list@pauillac.inria.fr using -f Received: from nez-perce.inria.fr (nez-perce.inria.fr [192.93.2.78]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id JAA23835 for ; Fri, 11 Oct 2002 09:52:45 +0200 (MET DST) Received: from mel-rto4.wanadoo.fr (smtp-out-4.wanadoo.fr [193.252.19.23]) by nez-perce.inria.fr (8.11.1/8.11.1) with ESMTP id g9B7qiD19975; Fri, 11 Oct 2002 09:52:44 +0200 (MET DST) Received: from mel-rta7.wanadoo.fr (193.252.19.61) by mel-rto4.wanadoo.fr (6.5.007) id 3DA24D320024F735; Fri, 11 Oct 2002 09:52:44 +0200 Received: from iliana (217.128.59.170) by mel-rta7.wanadoo.fr (6.5.007) id 3DA24BE60023AEC8; Fri, 11 Oct 2002 09:52:44 +0200 Received: from luther by iliana with local (Exim 3.36 #1 (Debian)) id 17zukb-0000Ww-00; Fri, 11 Oct 2002 10:02:25 +0200 Date: Fri, 11 Oct 2002 10:02:25 +0200 To: Xavier Leroy Cc: Sven LUTHER , Luc Maranget , "Scott J, " , caml-list@inria.fr Subject: Re: [Caml-list] Runtime overflow and what to do Message-ID: <20021011080225.GB1974@iliana> References: <00bd01c2706d$e7cd68e0$0100a8c0@janxp> <200210101521.RAA0000032708@beaune.inria.fr> <20021010181323.GA1922@iliana> <20021010205716.A8990@pauillac.inria.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20021010205716.A8990@pauillac.inria.fr> User-Agent: Mutt/1.4i From: Sven LUTHER Sender: owner-caml-list@pauillac.inria.fr Precedence: bulk On Thu, Oct 10, 2002 at 08:57:16PM +0200, Xavier Leroy wrote: > > But it is the lower bit that is ignored, no, si i guess incrementing an > > ocaml integer by 1, correspond to incrementing the machine integer by > > two, and would set the overflow flag in the processor status register > > all the same, would it not ? > > Yes, except that not all processors have overflow flags. The Alpha > and the MIPS don't, for instance. Integer arithmetic modulo a power Didn't know that. (Mostly i know about powerpc and M68K assembly only). Mmm, Is that why these processors are faster on number crunshing ? Or better said, a consequence of designing these processors fro being fast at number crunshing ? > of 2 is unpleasant for certain applications (and very useful for > others, e.g. hash functions and cryptography), but this is really all > what today's processors offer. Did you ever got hand on a MAJC processor, which supposedly has an extra bit for GC purpose, or something such ? Friendly, Sven Luther ------------------- To unsubscribe, mail caml-list-request@inria.fr Archives: http://caml.inria.fr Bug reports: http://caml.inria.fr/bin/caml-bugs FAQ: http://caml.inria.fr/FAQ/ Beginner's list: http://groups.yahoo.com/group/ocaml_beginners