From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from nez-perce.inria.fr (nez-perce.inria.fr [192.93.2.78]) by yquem.inria.fr (Postfix) with ESMTP id B6B1BBC3F for ; Sat, 30 Oct 2004 01:54:47 +0200 (CEST) Received: from pauillac.inria.fr (pauillac.inria.fr [128.93.11.35]) by nez-perce.inria.fr (8.13.0/8.13.0) with ESMTP id i9TNslh0002042 for ; Sat, 30 Oct 2004 01:54:47 +0200 Received: from concorde.inria.fr (concorde.inria.fr [192.93.2.39]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id BAA30912 for ; Sat, 30 Oct 2004 01:54:46 +0200 (MET DST) Received: from smtp1.adl2.internode.on.net (smtp1.adl2.internode.on.net [203.16.214.181]) by concorde.inria.fr (8.13.0/8.13.0) with ESMTP id i9TNsiIS025831 for ; Sat, 30 Oct 2004 01:54:45 +0200 Received: from [192.168.1.200] (ppp217-99.lns1.syd3.internode.on.net [203.122.217.99]) by smtp1.adl2.internode.on.net (8.12.9/8.12.9) with ESMTP id i9TNsb4Y075986; Sat, 30 Oct 2004 09:24:38 +0930 (CST) Subject: Re: [Caml-list] atomicity guarantees for threaded code From: skaller Reply-To: skaller@users.sourceforge.net To: David Brown Cc: Ker Lutyn , caml-list In-Reply-To: <20041029215027.GA9504@old.davidb.org> References: <20041029163907.36287.qmail@web40611.mail.yahoo.com> <20041029215027.GA9504@old.davidb.org> Content-Type: text/plain Message-Id: <1099094075.11063.215.camel@pelican.wigram> Mime-Version: 1.0 X-Mailer: Ximian Evolution 1.2.2 (1.2.2-4) Date: 30 Oct 2004 09:54:37 +1000 Content-Transfer-Encoding: 7bit X-Miltered: at nez-perce with ID 4182D847.001 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Miltered: at concorde with ID 4182D844.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Spam: no; 0.00; caml-list:01 sourceforge:01 wrote:01 wrote:01 threads:01 byte:01 alignment:01 sig:01 ocaml:01 threads:01 ocaml:01 bug:01 rtti:01 glebe:01 061:98 X-Spam-Checker-Version: SpamAssassin 3.0.0 (2004-09-13) on yquem.inria.fr X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=disabled version=3.0.0 X-Spam-Level: On Sat, 2004-10-30 at 07:50, David Brown wrote: > On Fri, Oct 29, 2004 at 09:39:07AM -0700, Ker Lutyn wrote: > > > thread 1: > > > > mapref := StringMap.add key value !mapref > > > > thread 2 through thread N: > > > > let value = StringMap.find key !mapref > > > > Assume only thread 1 can update the reference. Is this code safe? > > As long as the reference write is atomic, which it is going to be, I would > suspect this is safe. It probably would even be safe if multiple threads > updated the reference, but you might just drop entries. It isn't clear though. On x86 you can have 1 byte alignment for an address. What happens if: (a) thread 2 reads half an address, then gets a page fault (b) thread 1 writes half an address, then gets a page fault, (c) thread 1 writes the second half of the address (d) thread 2 reads the second half of the WRONG address The x86 can interrupt instructions in the middle *** Actually, the 68K can do this too. On the x86 the only way to get an atomic operation is on physical memory, and by also locking the bus. CISC machines get rather nasty .. Bottom line: you have to use a specified atomic access technique (eg sig_atomic_t, locks, etc) if you want to be sure an access is atomic. It is likely as you say that there won't be a problem on most processors (by which I mean the code Ocaml generates will be effectively atomic wrt. threads) and Ocaml could even guarrantee it, but there is a risk for some processor extra code would have to generated to ensure the guarrantee. *** And I mean even with IRQs. In particular I found a bug in the early 80186 hardware, where if you used two prefixes such as with ES REP MOVB then RTTI failed to restart the instruction correctly, setting the PC to the REP instead of the ES prefix. The MOVB instruction moves many bytes and must be interruptible, even on the 186 which has no VM. -- John Skaller, mailto:skaller@users.sf.net voice: 061-2-9660-0850, snail: PO BOX 401 Glebe NSW 2037 Australia Checkout the Felix programming language http://felix.sf.net